The present invention relates to clock timing calibration, and more particularly, to a clock timing calibration and clock timing calibration method for calibrating a phase difference between different clock signals (e.g., clock signals of a quantizer and digital-to-analog converters included in a continuous-time delta-sigma analog-to-digital converter) and related analog-to-digital conversion system using the same.
Delta-sigma analog-to-digital converters (ADCs) which use the delta-sigma modulation technique are commonly implemented in a variety of applications. For example, in a wireless communication transceiver, a continuous-time delta-sigma ADC is employed. FIG. 1 shows a diagram illustrating a conventional continuous-time delta-sigma ADC. The conventional continuous-time delta-sigma ADC 100 includes an adder 102 for subtracting an analog feedback signal A_FB from an analog input signal A_IN, a loop filter 104 (e.g., an integrator) for performing noise-shaping upon an output of the adder 102, a quantizer 106 (e.g., an ADC) for converting an output of the loop filter 104 into a digital output D_OUT with a quantization error added thereto, and a digital-to-analog converter (DAC) 108 for converting the digital output D_OUT into the analog feedback signal A_FB. In addition, the quantizer 106 is operated according to a quantizer clock signal CLK_1, and the DAC 108 is operated according to a DAC clock signal CLK_2.
Generally speaking, the conventional continuous-time delta-sigma ADC 100 has stringent requirement on excess loop delay. For example, the quantizer 106 has intrinsic delay on performing the quantization operation. In order to reduce the influence of the excess loop delay, a delay with one clock period could be introduced to the feedback loop between the quantizer clock signal CLK_1 and the DAC clock signal CLK_2. Please refer to FIG. 2, which shows a diagram illustrating another conventional continuous-time delta-sigma ADC. The continuous-time delta-sigma ADC 200 has a feedback delay stage 201 conceptually included therein to relax the excess loop delay problem mentioned above. The feedback delay stage 201 is schematically modeled between the output of the quantizer 106 and the input of the DAC 108. In an actual implementation, the feedback delay stage 201 is generally realized by delaying the quantizer clock timing with respect to the DAC clock timing by one clock period. As shown in FIG. 2, due to the implementation of the conceptual feedback delay stage 201 realized using clock timing adjustment, a compensation circuit (i.e., the DAC 208) is therefore needed to provide feedback compensation to the output of the loop filter 104. Specifically, before the output of the loop filter 104 is fed into the quantizer 106, the adder 202 disposed between the loop filter 104 and the quantizer 106 subtracts the feedback compensation generated from the DAC 208 from the output of the loop filter 104. As the operation and function of the DAC 208 which serves as the required compensation circuit are well known to those skilled in the art, further description is omitted here for brevity.
Ideally, the clock timing delay between the quantizer clock signal CLK_1 and the DAC clock signal CLK_2′ should be equal to one period; in other words, due to one period delay, the phase of the quantizer clock signal CLK_1 should be aligned with the phase of the DAC clock signal CLK_2′. However, in an actual implementation, such a clock timing requirement of the quantizer clock signal CLK_1 and the DAC clock signal CLK_2′ would necessitate the circuit elements included in the conventional continuous-time delta-sigma ADC to have critical circuit performance. For example, the bandwidth of the adder 202 should be as high as possible, and the intrinsic delay of the DAC 108 should be as small as possible. Under such a scenario, the circuit components in the conventional continuous-time delta-sigma ADC generally have high current consumption.